1. Field of the Invention
This invention relates generally to data transmission systems and, particularly, to a predictive clock recovery circuit having adaptive sampling determination means.
2. Description of the Prior Art
A data-communication system usually consists of three basic blocks: the transmitter, the channel, and the receiver. The transmitter has the task of assigning an electricical waveform to each possible sequence of digits received, at its input, from the data source. The electrical waveform is passed through the channel, and is invariably corrupted by unwanted, randoms signals known as noise. Because of these random signals, the received waveform does not correspond exactly to any of the possible transmitted waveforms. Nevertheless, the receiver must make a decision as to which of the data sequences is most likely to have given rise to the particular received waveform.
Particularly, the distribution of noise and intersymbol interference may readily be seen by using an oscilloscope to sweep out the received voltage corresponding to a baseband pulse transmission. The resulting oscilloscope display is widely known as an "eye pattern" from its resemblance to the human eye for binary data. To understand and interpret eye patterns, examine FIG. 1A and FIG. 1B where two bipolar waveforms are shown, one undistorted and the other distorted. In the undistorted waveform of FIG. 1A, a vertical line drawn through the center of the eye pattern shows a superposition of all received sampled values. When this sampling time is properly adjusted in FIG. 1A, all the sampled values are either +1, 0 or -1. In FIG. 1B, the waveform is distorted because of the effects of intersymbol interference and noise. Now, the signal received x(t) no longer passes through the proper values +1, -1 and 0 at each sampling point. The distorsion is clearly seen in the eye pattern for this waveform; the eye is now partially closed and detection is obviously more difficult. it should be noticed that the best sampling time must occur where the eye is open widest, that is to say in the middle of the eye pattern. Many receivers derive timing information by averaging zero crossings of the signal. The timing is adjusted to be halfway between crossing position. FIG. 1C illustrates such a conventional receiver: The analog signal x(t) received after the equalization process is transmitted to a peak detector 10 which determines the value Vp of the maximum amplitude of x(t). Then divide by 2 circuit 11 divides Vp by a given ratio, for instance 2. Comparator 12 receiving both signals x(t) and Vp has its output having a high level when x(t) is superior to Vp and conversely, a low level when x(t) is inferior to Vp. The signal at the output of comparator 12 is called the analog squared wave signal ASD. It is used to drive a phase locked oscillator PLO 13 which, by means of a internal clock of, generates a recovered clock in phase with ASD signal. The sampling timing is derived from the recovered clock by means of a delay circuit 14 which is adjusted to position approximately the timing in the "middle" of the eye opening.
In highly sophisticated receivers having powerful signal processing and egualization capabilities, the intersymbol interference is reduced to a minimum value and the eye pattern is very close to that of FIG. 1A. Consequently, in such systems, the clock recovery circuit described with respect to FIG. 1C is quite enough to allow good determination of the digit sequence. However, such systems must include signal processing means to allow an adaptive equalization of the transmission channel since the transmission characteristics may change to a large extent, particularly on telephone lines. When transmitting data at high speeds such as 56 kb/s, the signal processor must be particularly powerfull to allow an effective automatic equalization. For instance, a sophisticated equalization of a 56 kb/s communication channel requires a least a 14 Mips signal processor (millions of instructions per second). It is obviously noticed that the implementation of such means might increase considerably the overall cost of the receiver, particularly in low-cost bandbase equipments.
However, in such low cost equipments, such as a bandbase receiver, having no highly sophisticated equalization means, the eye pattern is rather closer to the eye of FIG. 1B than that of FIG. 1A, and particularly at high speeds. In such a system, it is much more fundamental to instruct sampling circuitry at optimal times, that is to say at the "middle" of the eye, whatever its distorsion is.
U.S. Pat. No. 4,339,823 describes an apparatus for generating a recovered clock signal having pulses with a selected transitory edge timed to occur at the center of the eye intervals of a multilevel digital signal. The system describes in that patent application includes a transition marker generating means, for generating a transition marker signal each time the received signal crosses any of a plurality of predetermined threshold levels. The transition marker generating means produces a plurality of transition marker signal groups, each transition marker signal group being followed in time by a eye interval. To assure that the sampling time will occur at the "middle of the eye", this system uses a particular phase error detection circuit 400 (column 10, line 45 and following). This circuit 400 is designed for counting the number of transition markers occurring during the high portion of each cycle of the recovered clock signal and the number of transition markers occurring during the low portion of each cycle of the recovered clock signal. Additional circuitry is used to generate a phase error signal when these quantities are not equal. However, this system involves complex design and analog circuitry for generating a sinusoidal signal, that will be difficult to integrate in a simple chip.
U.S. Pat. No. 4,295,222 describes an arrangement for restituting the clock and for sampling the demodulated signals formed by demodulation of the received signal by means of the signals which are in phase with and shifted through 90.degree. relative to a local carrier. This system comprises logic circuit to detect to which phase section out of n possible phase sections of the transmitted signals the phase of the received signal belongs at the sampling instants. It also involves a calculation to form the component which is in phase or shifted through 90.degree., of a signal derived form the received signal by means of a phase shift to make its phase equal, at the sampling instants, to the center phase of the detected phase section.
U.S. Pat. No. 4,335,825 also describes a clock extractor in which an input data signal is sampled and held in accordance with a sampling frequency. A difference in voltage is detected between those portions of a waveform obtained which appear before and after a time when the waveform has a maximum voltage amplitude. A phase of that portion of the waveform which has the maximum amplitude, is determined by making the above-mentioned difference equal to zero, and a clock signal synchronized with the portion having the maximum voltage amplitude is extracted and reproduced from the input data signal.
However, both preceeding patents involves complex processing of the received clock and moreover, these systems do not process inevitable erroneous transitions occurring in real received data flow. U.S. Pat. No. 3,851,101 describes an adaptive phase synchronizer for syncronizing the phase of received digital data with the phase of a local clock. This system includes means for taking multiple samples of each bit of the received data, modulo 2 adders and up-down counters for locating the transitions in the data bits, and phase correcting means responsive to said transitions for adjusting the phase of the data over a range in excess of one bit intervals in accordance with the locations of the transitions in the received data relative to the local pulses. The system also includes a sampling register having a number of stages and a phase synchronizing circuit having more stages than that of the sampling register. Predetermined ones of the stages of the phase synchronizing register are selected depending upon the initial location of the transition in the sampling register. The stages are selected such that the transition occurs near the center of the group of stages selected. However, even if this system includes means for ignoring erroneous transitions (more than one per bit), it is complex and involves multiple samples of each bit.